“Effective Minimization of Charge-trapping in High-k gate Dielectrics with an Ultra-short Pulse Technique,” 7th International Conference on Solid-State and Integrated Circuits Technology. 1, p.470, 2004

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“Pulsed Id-Vg methodology and its application to electron trapping characterization and defect density profiling,” IEEE Trans. On Electron Device, 56(6), p.1322, Jun. 2009.

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“Probing stress effects in HfO2 gate stacks with time dependent measurements,” Microelectronics and Reliability, vol. 45, No. 5-6, p. 806, 2005

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