“A novel electrode induced strain engineering for High performance SOI finFET utilizing Si(110) channel for both nMOS and pMOS,” Tech. Dig. of IEDM, 2006.

Download

“Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration”, Proc. of symposium on VLSI technology, p.10, 2006.

Download

“Detection of Trap Generation in High-k Gate Stacks by Constant Voltage Stress due to constant voltage stress”, Proc. of VLSI-TSA, 2006.

“Detection of Electron Trap Generation Due to Constant Voltage Stress on High-κ Gate Stacks”, Proc. of IRPS, p.169 , 2006.

Download

“Detection of Trap Generation in High-k Gate Stacks due to Constant Voltage Stress,” Proc. of Int. Integrated Rel. Workshop, p.78, 2005.

“Impacts of Si Concentration in Hf-silicate on Performance and Reliability of Metal Gate CMOSFET,” Ext. Abs. of Symp. on Solid State Device and Materials, 2005.