글
https://gistexel.com/wp-content/uploads/2014/08/logo_exel.gif
0
0
exel
https://gistexel.com/wp-content/uploads/2014/08/logo_exel.gif
exel2014-09-02 16:51:002014-09-02 16:51:04"Dipole Model Explaining High-k/Metal Gate Threshold Voltage Tuning",Electrochem. Soc. Transaction, 19(1), p.269, 2009. (Invited)
https://gistexel.com/wp-content/uploads/2014/08/logo_exel.gif
0
0
exel
https://gistexel.com/wp-content/uploads/2014/08/logo_exel.gif
exel2014-09-02 16:35:382014-09-02 16:35:42 “Flexible, simplified CMOS on Si(110) with Metal Gate/High-k for HP and LSTP”,Tech. Dig. of IEDM, p.57, 2007.
https://gistexel.com/wp-content/uploads/2014/08/logo_exel.gif
0
0
exel
https://gistexel.com/wp-content/uploads/2014/08/logo_exel.gif
exel2014-09-02 16:32:172014-09-02 16:32:20 “Metal Gate Induced Strain Engineering for High-k/Metal Gate MOSFETs,” Proc. of 4th Int. Symp. on Adv. Gate Stack Tech., 2007.
https://gistexel.com/wp-content/uploads/2014/08/logo_exel.gif
0
0
exel
https://gistexel.com/wp-content/uploads/2014/08/logo_exel.gif
exel2014-09-02 16:03:282014-09-02 16:03:35“A novel electrode induced strain engineering for High performance SOI finFET utilizing Si(110) channel for both nMOS and pMOS,” Tech. Dig. of IEDM, 2006.
https://gistexel.com/wp-content/uploads/2014/08/logo_exel.gif
0
0
exel
https://gistexel.com/wp-content/uploads/2014/08/logo_exel.gif
exel2014-09-02 15:57:282014-09-02 15:57:47“Effects of ALD TiN Metal Gate Thickness on Metal Gate /High-k Dielectric SOI FinFET Characteristics”, IEEE SOI Conference, 2006.
https://gistexel.com/wp-content/uploads/2014/08/logo_exel.gif
0
0
exel
https://gistexel.com/wp-content/uploads/2014/08/logo_exel.gif
exel2014-09-02 15:50:572014-09-02 15:51:00“Compatibility of ALD HfSiON with Dual Metal Gate CMOS Integration ”, Ext. Abs. of SSDM, p.1114, 2006.
