“Improved Flash Memory Program and Erase Window with TiO2 Charge Trap Layer and High Temperature Dopant Activation Anneal,” Proc. of 4th Int. Symp. on Adv. Gate Stack Tech., 2007.

“Band Edge n-MOSFETs with High-k/Metal Gate Stacks Scaled to EOT=0.9nm with Excellent Carrier Mobility and High Temperature Stability,” Tech. Dig. of IEDM, 2006.

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“High Mobility HfSiON Gate Dielectric for High Performance Applications with Minimal Charge Trapping and Suppressed Crystallization,” Tech. Dig. of IEDM, p.437, 2005.

“Mobility and Charge Trapping Comparison for Crystalline and Amorphous HfON and HfSiON Gate Dielectrics”, Appl. Phys. Lett., 89, 242909, 2006.

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