“Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High-k/Metal Gate Stacks Directly on SiGe and a Method to Enable Sub-1nm EOT”, Proc. Of Symp. On VLSI Technology, p.92, 2008.

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“Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme,” Proc. of Symp. on VLSI Tech., p.154, 2007

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“Effect of Si capping layer on the interface quality and NBTI of high mobility channel Ge-on-Si pMOSFETs,“ Microelectronics Eng. 86(3), p.259, Mar. 2009.

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“New Hot-Carrier Injection Mechanism at Source Side in Nanoscale Floating-Body MOSFETs, “ IEEE Elect. Dev. Lett., 30(1), p.54-56, Jan. 2009.

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“Effective surface passivation methodologies for high performance germanium Metal Oxide Semiconductor Field Effect Transistors,” Appl. Phys. Lett., 93. p.192115, Nov. 2008.

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“Effect of Si interlayer thickness and post-metallization annealing on Ge MOS capacitor on Ge-on-Si substrate,” Materials Science and Engineering B, 154, p.102-105, 2008.

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