“Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme,” Proc. of Symp. on VLSI Tech., p.154, 2007

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“Dipole Model Explaining High-k/Metal Gate Field Effect Transistor Threshold Voltage Tuning,” Appl. Phys. Lett. 92, 092901, Mar. 2008

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