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exel
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exel2014-09-02 10:05:532014-09-02 10:05:56 "Advanced Integration Technology for a Highly Scalable SOI DRAM with SOC(Silicon-On-Capacitor),” Tech. Dig. of IEDM, p.605,1996
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exel2014-09-02 10:03:252014-09-02 10:03:32"A Novel CMP Method for Cost-effective Bonded SOI Wafer fabrication,” Proceedings of 21st IEEE International SOI Conference, pp. 60-61, 1995.
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exel2014-09-01 10:22:172014-09-01 10:22:48 “Comparison of Low Frequency Noise in Channel and Gate Induced Drain Leakage Currents of High-k nFETs,” IEEE Elect. Dev. Lett., 31., 10, p.1086-1088, Oct. 2010.
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exel2014-08-29 11:07:282014-08-29 11:07:53"Design Consideration for Patterned Wafer Bonding,” Jpn. J. Appl. Phys., 36, p.1912-1916, 1997
