“Advanced Integration Technology for a Highly Scalable SOI DRAM with SOC(Silicon-On-Capacitor),” Tech. Dig. of IEDM, p.605,1996

Download

“A Novel CMP Method for Cost-effective Bonded SOI Wafer fabrication,” Proceedings of 21st IEEE International SOI Conference, pp. 60-61, 1995.

Download

“Comparison of Low Frequency Noise in Channel and Gate Induced Drain Leakage Currents of High-k nFETs,” IEEE Elect. Dev. Lett., 31., 10, p.1086-1088, Oct. 2010.

Download