“Dipole Model Explaining High-k/Metal Gate Threshold Voltage Tuning”,Electrochem. Soc. Transaction, 19(1), p.269, 2009. (Invited)

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“Device and Reliability Improvement of HfSiON+LaOx/Metal Gate Stacks for 22nm Node Application”, Proc. of Int. Electron Device Meeting, p.45, 2008.

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“The Effects Of Ge Composition And Si Cap Thickness On Hot Carrier Reliability Of Si/Si1-XGex/Si P-MOSFETS With High-K/Metal Gate”, Proc. Of Symp. On VLSI Technology, p.56, 2008

“Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High-k/Metal Gate Stacks Directly on SiGe and a Method to Enable Sub-1nm EOT”, Proc. Of Symp. On VLSI Technology, p.92, 2008.

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