“A Novel Damage-Free High-k Etch Technique Using Neutral Beam Assisted Atomic Layer Etching (NBALE) for sub-32nm Technology Node Low Power Metal Gate/High-K Dielectric CMOSFETs”, Proc. of Int. Elect. Dev. Meeting, 2009

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“Dipole Model Explaining High-k/Metal Gate Threshold Voltage Tuning”,Electrochem. Soc. Transaction, 19(1), p.269, 2009. (Invited)

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“Device and Reliability Improvement of HfSiON+LaOx/Metal Gate Stacks for 22nm Node Application”, Proc. of Int. Electron Device Meeting, p.45, 2008.

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“Mechanisms of Oxygen and Hydrogen Passivation using High Pressure Post-annealing Processes to Enhance the Performance of MOSFETs with Metal Gate/High-k Dielectric, “ Ext. Abs. of Symp. On Solid State Device and Materials, p.22, 2008.