“Dipole Model Explaining High-k/Metal Gate Threshold Voltage Tuning”,Electrochem. Soc. Transaction, 19(1), p.269, 2009. (Invited)

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“The Impact of La-Doping on the Reliability of Low Vth High-k/Metal Gate nMOSFETs Under Various Gate Stress Conditions”, Proc. of Int. Electron Device Meeting, p.115, 2008.

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“Plasma induced damage of aggressively scaled gate dielectric (EOT < 1.0 nm) in metal gate/high-k dielectric CMOSFETs,” Proc. of IRPS, 2008.

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“A comparative study of reliability and performance of strain engineering using CESL stressor and mechanical strain,” Proc. of IRPS, 2008.

“Tunnel Oxide Dipole Engineering in TANOS Flash Memory for Fast Programming with Good Retention and Endurance,” Proc. of VLSI-TSA, 2008.

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