“CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture ,” US patent No.6891228 and No. 6828630, 2005.

/카테고리: /작성자:
다음의 항목 또한 추천합니다.
“Method for measuring capacitance”, U.S. patentNo. 6828630, 2009.06.16
“Forming gate oxide having multiple thickness,” U.S. patent No. 7,160,771, 2007.
“Triple layer hard mask for gate patterning to fabricate scaled transistor,” US patent No.6800530, 2004
“ Integration of dual workfunction metal gate CMOS devices,” US patent No. 6653698, 2003.
"Apparatus and methods for wafer debonding using a liquid jet,” US patent No.5783022, 1998.
"Wafer polishing device,” US patent No.5735731, 1998.