“Enhanced Surface Preparation Techniques for the Si/High-k Interface,” UCPSS, 2004

/카테고리: /작성자:
다음의 항목 또한 추천합니다.
"Dipole Model Explaining High-k/Metal Gate Threshold Voltage Tuning",Electrochem. Soc. Transaction, 19(1), p.269, 2009. (Invited)
"Device and Reliability Improvement of HfSiON+LaOx/Metal Gate Stacks for 22nm Node Application", Proc. of Int. Electron Device…
“The Impact of La-Doping on the Reliability of Low Vth High-k/Metal Gate nMOSFETs Under Various Gate Stress…
“Breakdown in the metal/high-k gate stack: Identifying the “weak link" in the multilayer dielectric,” Proc. of Int.…
“Gate stack technology for nano-scale CMOS devices,”, Int. MRS, Chongging, China, 2008. (Invited)
“Gate stack technology for nano-scale CMOS devices,”, IWDTF, Tokyo. Japan, 2008. (Invited)