“Compatibility of ALD HfSiON with Dual Metal Gate CMOS Integration ”, Ext. Abs. of SSDM, p.1114, 2006.

/카테고리: /작성자:
다음의 항목 또한 추천합니다.
“Method for measuring capacitance”, U.S. patentNo. 6828630, 2009.06.16
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“CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture ,” US…
“Triple layer hard mask for gate patterning to fabricate scaled transistor,” US patent No.6800530, 2004
“ Integration of dual workfunction metal gate CMOS devices,” US patent No. 6653698, 2003.
"Apparatus and methods for wafer debonding using a liquid jet,” US patent No.5783022, 1998.