Highly Manufacturable Advanced Gate Stack Technology for Sub 45nm Self-Aligned Gate-First CMOSFETs,” IEEE Trans. on Elec. Dev. 53, p.979, 2006. (Invited)

/카테고리: /작성자:

Download

다음의 항목 또한 추천합니다.
“Characterization of ultra-thin dielectric using time domain reflectometry" presented at Int. Workshop on Dielectric Thin Films. (IWDTF)…
“Interfacial defects at top gate graphene FETs investigated using a novel discharging current measurement method”, presented at…
“Highly sensitive Al2O3 passivated CVD graphene photodetectors for UV to IR region”, presented at Int. Workshop on…
“Reliability characteristics of MoS2 FETs,” Int. Conf. on Solid State Device and Materials(SSDM), 2013.
” Comprehensive Study for RF Interference Limited 3D TSV Optimization”, Proc. of VLSI-TSA , April, 2013
“Sub-10nm1T-1R Cell Design using HfOx based ReRAM Cell”, Proc. of VLSI-TSA, April, 2013.